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1998.11.30 Ver.B
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change.
M5M54R16AJ,ATP-10,-12,-15
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M54R16A is a family of 262144-word by 16-bit static RAMs, fabricated with the high performance CMOS process and designed for high speed application. These devices operate on a single 3.3V supply, and are directly TTL compatible. They include a power down feature as well. In write and read cycles, the lower and upper bytes are able to be controled either togethe or separately by LB and UB.
CHIP SELECT INPUT DATA INPUTS/ OUTPUTS ADDRESS INPUTS
PIN CONFIGURATION (TOP VIEW)
FEATURES
*Fast access time M5M54R16AJ,ATP-10 ... 10ns(max) M5M54R16AJ,ATP-12 ... 12ns(max) M5M54R16AJ,ATP-15 ... 15ns(max)
A0 A1 A2 A3 A4 S DQ1 DQ2 DQ3 DQ4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
*Single +3.3V power supply *Fully static operation : No clocks, No refresh *Common data I/O *Easy memory expansion by S *Three-state outputs : OR-tie capability *OE prevents data contention in the I/O bus *Directly TTL compatible : All inputs and outputs *Separate control of lower and upper bytes by LB and UB
GND DQ5 DATA DQ6 INPUTS/ DQ7 OUTPUTS DQ8 WRITE CONTROL INPUT W A5 A6 ADDRESS INPUTS A7 A8 A9
(3.3V) (0V)
VCC
A17 ADDRESS A16 INPUTS A15 OUTPUT OE ENABLE INPUT BYTE UB CONTROL LB INPUTS DQ16 DQ15 DATA INPUTS/ DQ14 OUTPUTS DQ13 GND (0V)
VCC
DQ12 DQ11 DQ10 DQ9 N.C A14 A13 A12 A11 A10
(3.3V)
DATA INPUTS/ OUTPUTS
ADDRESS INPUTS
Outline
44P0K
APPLICATION
High-speed memory system
PACKAGE
M5M54R16AJ .......... 44pin 400mil SOJ M5M54R16ATP .......... 44pin 400mil TSOP(II) state. (LB and/or UB=L, S=L) When setting LB at a high level and other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enable, and lower-Byte are in a non-selectable mode. And when setting UB at a high level and other pins are in an active state, lower-Byte are in a selectable mode in which both reading and writing are enable, and upperByte are in a non-selectable mode. When setting LB and UB at a high level or S at high level, the chip is in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by LB, UB and S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time.
FUNCTION
The operation mode of the M5M54R16A is determined by a combination of the device control inputs S, W, OE, LB, and UB. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with low level LB and/or low level UB and low level S. The address must be set-up before write cycle and must be stable during the entire cycle. The data is latched into a cell on the traling edge of W, LB, UB or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while LB and/or UB and S are in an active
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
M5M54R16AJ,ATP-10,-12,-15
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION TABLE
S L L L L L L L L H W H H H L L L H X X OE L L L X X X H X X LB L H L L H L X H X UB L L H L L H X H X Mode Read cycle All Bytes Read cycle Upper Bytes Read cycle Lower Bytes Write cycle All Bytes Write cycle Upper Bytes Write cycle Lower Bytes Output disable Non selection DQ1~8 D OUT High-impedance D OUT D IN High-impedance D IN High-impedance High-impedance DQ9~16 D OUT D OUT High-impedance D IN D IN High-impedance High-impedance High-impedance Icc Active Active Active Active Active Active Active Stand by
BLOCK DIAGRAM
ADDRESS INPUTS
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 S W OE UB LB
1 2 3 4 5 18 19 20 21 22
MEMORY ARRAY 1024 ROWS 4096 COLUMNS
7 8 9 10 13 14 15 16
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DATA INPUTS/ OUTPUTS
CHIP SELECT INPUT WRITE CONTROL INPUT OUTPUT ENABLE INPUT UPPER BYTE CONTROL INPUT LOWER BYTE CONTROL INPUT
6 17
COLUMN I/O CIRCUITS COLUMN ADDRESS DECODERS COLUMN INPUT BUFFERS
29 30 31 32 35 36 37 38
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16
DATA INPUTS/ OUTPUTS
41
40
11 33 12
VCC
(3.3V)
39 23 24 25 26 27 42 43 44
34
GND (0V)
A10 A11A12 A13 A14 A15A16A17
ADDRESS INPUTS
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MITSUBISHI LSIs
M5M54R16AJ,ATP-10,-12,-15
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol V cc VI VO Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND Ta=25C Ratings - 2.0*~ 4.6 - 2.0*~ Vcc+0.5 - 2.0*~ Vcc 1000 0 ~ 70 - 10 ~ 85 - 65 ~ 150 Unit V V V mW C C C
Pd T opr Tstg(bias) Storage temperature(bias) Tstg
*Pulse width 3ns, In case of DC: - 0.5V
DC ELECTRICAL CHARACTERISTICS
Symbol VIH VIL VOH VOL II IOZ Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Output current in off-state Active supply current (TTL level)
(Ta=0~70C, Vcc=3.3V Condition
+10% -5% ,unless
otherwise noted) Min 2.0 2.4 0.4 2 2 Limits Typ Max Vcc+0.3 0.8 Unit V V V V uA uA
IOH = - 4mA IOL= 8mA V I = 0 ~ Vcc VI (S)= VIH VO= 0 ~ Vcc VI (S)= VIL other inputs VIH or VIL Output-open(duty 100%) AC(10ns cycle) AC(12ns cycle) AC(15ns cycle) DC AC(10ns cycle) AC(12ns cycle) AC(15ns cycle) DC
I CC1
I CC2
Stand-by supply current (TTL level) Stand-by current (MOS level)
VI (S)= VIH VI (S)= Vcc - 0.2V other inputs VI0.2V or VIVcc - 0.2V
260 250 230 120 90 70 60 40 10
mA
mA
I CC3
mA
Note 1: Direction for current flowing into an IC is positive (no mark).
CAPACITANCE
Symbol
(Ta=0~70C , Vcc=3.3V Parameter
+10% -5%
,unless otherwise noted) Test Condition Min Limit Typ Max 7 8 Unit pF pF
CI Input capacitance VI =GND,Vi =25mVrms,f=1MHz CO Output capacitance Vo =GND,Vo =25mVrms,f=1MHz Note 2: CI,CO are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS (Ta= 0~70 C ,VCC=3.3V +10% ,unless otherwise noted) -5%
(1) MEASUREMENT CONDITION
Input pulse levels ................................... VIH=3.0V,VIL=0.0V Input rise and fall time ................................................... 3ns Input timing reference levels ...................... VIH=1.5V,VIL=1.5V Output timing reference levels ................ VOH=1.5V, VOL=1.5V Output loads ....................................................... Fig1 ,Fig2
OUTPUT Z0=50 5.0V 480 DQ RL=50 VL=1.5V Fig.1 Output load DQ 255 5pF Including
( scope and JIG )
Fig.2 Output load for t en, t dis
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MITSUBISHI LSIs
M5M54R16AJ,ATP-10,-12,-15
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
READ CYCLE
Limits
Symbol Parameter M5M54R16AJ,ATP-10 M5M54R16AJ,ATP-12M5M54R16AJ,ATP-15 Unit
tCR ta(A) ta(S) ta(OE) ta(B) tdis(S) tdis(OE) tdis(B) ten(S) ten(OE) ten(B) tv(A) tPU tPD
Read cycle time Address access time Chip select access time Output enable access time LB,UB access time Output disable time after S high Output disable time after OE high Output disable time after LB,UB high Output enable time after S low Output enable time after OE low Output enable time after LB,UB low Data valid time after address change Power-up time after chip selection Power-down time after chip selection
Min 10
Max 10 10 5 5 5 5 5
Min 12
Max 12 12 6 6 6 6 6
Min 15
Max 15 15 7 7 7 7 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
0 0 0 2 0 0 2 0
0 0 0 3 1 1 3 0
0 0 0 3 1 1 3 0
10
12
15
Write cycle
Limits
Symbol Parameter M5M54R16AJ,ATP-10 M5M54R16AJ,ATP-12 M5M54R16AJ,ATP-15 Unit
Min tCW tw(W) tw(W) tsu(B) tsu(A)1 tsu(A)2 tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) ten(B) tsu(A-WH) tsu(A-SH) tsu(A-BH)
Write cycle time Write pulse width (OE low) Write pulse width(OE high) LB,UB setup time Address setup time(W) Address setup time(S) Chip select setup time Data setup time Data hold time Write recovery time Output disable time after W low Output disable time after OE high Output enable time after W high Output enable time after OE low Output enable time after LB,UB low Address to W High Address to S High Address to LB,UB High
Max
10 10 8 8 0 0 8 5 0 1 0 0 0 0 0 8 8 8 5 5
Min 12 12 10 10 0 0 10 6 0 1 0 0 0 0 0 10 10 10
Max
Min 15 15 10 10 0 0 10 7 0 1 0 0 0 0 0 10 10 10
Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
6 6
7 7
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MITSUBISHI LSIs
M5M54R16AJ,ATP-10,-12,-15
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS Read cycle 1 A 0~17
VIH VIL
t CR
ta(A) tv(A) tv(A)
UNKNOWN DATA VALID PREVIOUS DATA VALID
DQ1~16
VOH VOL W=H S=L OE=L
LB=L UB=L
Read cycle 2 (Note 3)
t
CR
S
VIH VIL
ta(S) ten(S)
(Note 4)
tdis(S)
(Note 4)
DQ1~16
VOH VOL
UNKNOWN
DATA VALID
tPU
tPD
50% 50%
Icc
ICC1 ICC2 W=H UB=L
OE=L LB=L
Note 3. Addresses valid prior to or coincident with S transition low. 4. Transition is measured 500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 5) OE
VIH VIL
t CR
(Note 4)
ta(OE)
(Note 4)
tdis(OE)
ten(OE)
UNKNOWN DATA VALID
DQ1~16
VOH VOL W=H S=L UB=L LB=L
Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
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MITSUBISHI LSIs
M5M54R16AJ,ATP-10,-12,-15
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Read cycle 4 (Note 6) UB,LB
VIH VIL
t CR
(Note 4)
ta(B)
(Note 4)
tdis(B)
ten(B)
UNKNOWN DATA VALID
DQ1~16
VOH VOL W=H S=L OE=L
Note 6. Addresses , S and OE valid prior to LB,UB transition low by (ta(A)-ta(B)), (ta(S)-ta(B)), (ta(OE)-ta(B)).
Write cycle (W control mode)
t CW
A 0~17 S
VIH VIL VIH VIL
tsu(S)
(Note 7) (Note 7)
tsu(A-WH)
OE
VIH VIL
tsu(A)
tw(W)
trec(W)
W
VIH VIL
tsu(B)
LB,UB
VIH VIL
(Note 7)
(Note 7)
tsu(D) th(D)
DQ1~16
(Input Data)
VIH VIL
DATA STABLE
tdis(W) tdis(OE)
(Note 4)
ten(OE) ten(W)
Hi-Z
(Note 4)
DQ1~16
(Output Data)
VOH VOL
Note 7: Hatching indicates the state is don't care. 8: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance. 9: ten,tdis are periodically sampled and are not 100% tested.
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MITSUBISHI LSIs
M5M54R16AJ,ATP-10,-12,-15
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle(S control)
t CW
A 0~17
VIH VIL
tsu(A)
tsu(A-SH) tsu(S)
trec(W)
S W
VIH VIL
tw(W)
VIH VIL
(Note 6) (Note 6)
tsu(B)
LB,UB
VIH VIL
(Note 6) (Note 6)
tsu(D)
th(D)
DQ1~16
(Input Data)
VIH VIL
(Note 4)
DATA STABLE
DQ1~16
(Output Data)
VOH VOL
ten(S)
tdis(W) ten(B)
(Note 4)
Hi-Z
(Note 8)
Write cycle(LB,UB control)
t CW
A 0~17
VIH VIL
tsu(S)
S W
VIH VIL
(Note 6) (Note 6)
tw(W)
VIH VIL
(Note 6)
tsu(A)
tsu(A-BH) tsu(B)
(Note 6)
trec(W)
LB,UB
VIH VIL
tsu(D)
th(D)
DQ1~16
(Input Data)
VIH VIL
DATA STABLE
tdis(W)
(Note 4)
(Note 4)
DQ1~16
(Output Data)
VOH VOL
ten(B)
ten(S)
Hi-Z
(Note 8)
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